Every time a user interACTs with an AI model like ChatGPT, a high-stakes data relay race begins. Information must leave memory, travel to a CPU for preprocessing, move to a GPU for heavy computation, and then return. This inefficient journey repeats for every single word generated, creating a structural bottleneck that routes data through some of the industry's most expensive and power-hungry components.
XCENA, a four-year-old startup with offices in South Korea and the United States, is on a mission to solve this inefficiency. The company has designed a novel chip architecture that places compute capabilities directly adjacent to DRAM (the fast, short-term memory used for active data). This allows routine data Operations to be handled near the memory itself, eliminating costly round trips between CPUs, GPUs, and memory modules.
A Major Bet on Memory-Centric AI
Investor enthusiasm for this "memory-centric" APProach is evident. XCENA recently closed a $135 million Series B round at a $570 million Valuation, bringing its total capital raised to $185 million.
Investor enthusiasm for this "memory-centric" APProach is evident. XCENA recently closed a $135 million Series B round at a $570 million Valuation, bringing its total capital raised to $185 million.
The startup is led by CEO Jin Kim, CTO Dohun Kim, and CPO HARRy Juhyun Kim, all veterans of memory giants Samsung and SK Hynix. "CPUs and GPUs have both gotten smarter over the decades, but memory never did. XCENA wants to change that," Jin Kim stated in an interview. He noted that the recent surge in memory prices and the historic trillion-dollar valuations of Samsung, SK Hynix, and Micron signal a massive infrastructure shift.
XCENA operates on the thesis that AI Inference is no longer just a compute problem—it is increasingly a memory scaling problem.
How the MX1 Chip Works
XCENA’s flagship chip, the MX1, connects to the CPU via CXL (Compute Express Link)—a high-speed interconnect that acts as an express lane between the processor and memory. By processing data before it ever leaves the memory module, the MX1 brings the compute to the data, rather than the other way around. The company claims this efficiency could allow workloads that currently require 10 servers to run on just one.
XCENA’s flagship chip, the MX1, connects to the CPU via CXL (Compute Express Link)—a high-speed interconnect that acts as an express lane between the processor and memory. By processing data before it ever leaves the memory module, the MX1 brings the compute to the data, rather than the other way around. The company claims this efficiency could allow workloads that currently require 10 servers to run on just one.
"While GPUs excel at the heavy math of matrix multiplication, much of the surrounding data orchestration—such as preprocessing, KV cache management, and data caching—still relies on CPUs," Kim explained. "Our chip handles those tasks directly within the memory module."
strategic Positioning and Technology
XCENA is targeting the memory-intensive layer beneath the AI training workloads dominated by NVIDIA. While rivals like Astera Labs and Marvell are also advancing memory connectivity, XCENA differentiates itself through its Intellectual property and architecture.
XCENA is targeting the memory-intensive layer beneath the AI training workloads dominated by NVIDIA. While rivals like Astera Labs and Marvell are also advancing memory connectivity, XCENA differentiates itself through its Intellectual property and architecture.
"We have thousands of cores," Kim noted, contrasting their approach with Marvell’s reliance on a handful of General-purpose cores. XCENA’s architecture is built on RISC-V, an open-source blueprint, optimized specifically for data processing. The company maintains a high level of vertical integration by designing its own internal memory hierarchy, interconnect bus, and DRAM controller.
Roadmap and future Outlook
Demand for advanced memory solutions has surged since late last year, putting XCENA in a favorable position. The company is currently in early-stage discussions with global memory vendors and is targeting hyperscalers—tech giants spending billions on AI infrastructure where even minor efficiency gains translate to massive cost savings.
Demand for advanced memory solutions has surged since late last year, putting XCENA in a favorable position. The company is currently in early-stage discussions with global memory vendors and is targeting hyperscalers—tech giants spending billions on AI infrastructure where even minor efficiency gains translate to massive cost savings.
Currently, the MX1 is in the prototype stage. Mass production is scheduled to begin at Samsung’s foundries by the end of 2026, with revenue generation expected to start in 2027.
The Series B round was co-led by Seoul-based VC firms Altinum and IMM Investment, alongside Corstone Asia and existing investors SBI investment and Mirae Asset Capital. With over 90 employees across Pangyo (South Korea) and Sunnyvale (USA), XCENA is also in talks with international investors for further funding.
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