World Model First Guides Chip Design: Ultra-Large Core NPU with 700 TOPS and 99% Usable Compute

A new chip design leverages a world model for the first time to guide the design process, resulting in an ultra-large core NPU with 700 TOPS of AI compute and 99% usable compute efficiency. This marks a significant milestone in applying world models to hardware design, potentially improving performance and reducing design complexity. The chip's high usable compute ratio addresses common inefficiencies in AI accelerators.